Delay circuits are ubiquitous in digital integrated circuits. They are used, for example, to ensure two clock lines of different lengths (and therefore different signal propagation times) deliver their respective clock signals contemporaneously.
FIG. 1 shows a conventional delay circuit 100 for producing a desired delay time when an input signal (Vin) changes between logic levels. Delay circuit 100 includes a first compensating circuit 1 for NMOS transistors, a second compensating circuit 2 for PMOS transistors, and four inverter stages I1, I2, I3, and I4. Inverters I2 and I4 include respective NMOS transistors N2 and N5, each receiving as a gate signal an output signal NO from compensating circuit 1 and connected in series to the respective sources of NMOS transistors N3 and N6. Inverters I1 and I3 include respective PMOS transistors P2 and P5 receiving as a gate signal an output signal PO from compensating circuit 2 and connected in series to the respective sources of PMOS transistors P1 and P4.
FIG. 2A is a circuit diagram showing compensating circuit 1 for NMOS transistors. Compensating circuit 1 includes a resistor R1 and an NMOS transistor N7 connected in series between the power-source voltage Vcc and ground. An output signal NO is supplied from the connection point between the resistor R1 and the transistor N7. The gate signal CE (chip enable) of NMOS transistor N7 is the power-supply voltage Vcc in operation.
Compensation circuit 1 compensates for changes in transistor threshold voltages V.sub.TH that affect all transistors and that occur due to process variations. As V.sub.TH decreases, the on impedance of NMOS transistor N7 decreases, lowering the potential of output signal NO to the gates of transistors N2 and N4. Thus, when V.sub.TH is relatively small, a reduction in the gate voltage on transistors N2 and N4 offsets the decrease in on-impedances of transistors N2 and N4 due to the small V.sub.TH. The circuit functions in the opposite manner when V.sub.TH is relatively large. In this way, compensating circuit 1 maintains a relatively constant delay time for each of inverters I2 and I4.
FIG. 2B is a circuit diagram showing compensating circuit 2 for PMOS transistors. The second compensating circuit 2 includes a PMOS transistor P7 and a resistor R2 connected in series between the power-source voltage Vcc and ground. An output signal PO is supplied from the connection point between the transistor P7 and the resistor R2. The gate signal /CE (chip-enable not) of PMOS transistor P7 is at the ground potential in operation. Compensation circuit 2 operates substantially as described above in connection with compensation circuit 1. A description of the operation of compensation circuit 2 is therefore omitted for brevity.
The compensation circuits of delay circuit 100 compensate for changes in the delay period of delay circuit 100 that normally occur due to process variations. However, Circuit 100 is still sensitive to temperature and supply-voltage variations that can induce undesirable changes in the delay period. Voltage NO of FIG. 2A is a function of the supply voltage Vcc, the resistance R1, and the characteristics of transistor N7. Changes in the transistor characteristics of transistor N7 that result from temperature variations may be compensated for by similar changes in transistors N2 and N5; however, resistor R1 may also be affected by a change in temperature, and this will change the voltage of NO in a manner that is not compensated for in circuit 100. Consequently, the delay of circuit 100 may change. Voltage supply variation will likewise affect the voltage NO in a way that is not compensated for in circuit 100, thus further affecting the delay. An analogous situation exists for voltage PO, transistor P7, and resistor R2 of FIG. 2B, and transistors P2 and P5 of FIG. 1.
Another potential problem associated with delay circuit 100 is that the delay imposed on the positive-going portion of the input signal can differ from that of the negative-going portion of the input signal because separate compensation circuits are used to establish the reference voltages for the respective PMOS and NMOS transistors. There therefore remains a need for delay circuits that are less sensitive to temperature and supply-voltage fluctuations.